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The VAX 8000 was a family of minicomputers developed and manufactured by Digital Equipment Corporation (DEC) using processors implementing the VAX instruction set architecture (ISA). == VAX 8600 == The VAX 8600, code-named "''Venus''", introduced in October 1984, was the successor of the VAX-11/785. It was originally to be named "VAX-11/790", but was renamed before launch. The VAX 8600 was a successful model and at the time was the best selling high-end VAX. It was succeeded by the VAX 8800 family in 1987. The VAX 8600 had a CPU with an 80 ns cycle time (12.5 MHz) implemented with emitter coupled logic (ECL) macrocell arrays (MCAs). The CPU consisted of four major logical sections, the E Box, F Box, I Box and M Box. The E Box executed all instructions, including floating-point instructions through microcode. It had an arithmetic logic unit (ALU) and barrel shifter. The F Box, or floating point accelerator (FPA), was an optional feature that accelerated floating-point instructions as well as integer multiplication and division. It was a two-module set consisting of an adder module and multiplier module. The adder module contained 24 macrocell arrays while the multiplier module contained 21. The I Box fetched and decoded instructions. The M Box controlled the memory and I/O, translated virtual addresses to physical addresses and contained a 16 KB data cache. The CPU used 145 MCAs. These were large scale integration devices fabricated by Motorola in their 3 µm MOSAIC bipolar process. They were packaged in 68-pin leadless chip carriers or pin grid arrays and were mounted onto the printed circuit board in sockets or were soldered in place. An additional 1,100 small scale integration (SSI) and medium scale integration (MSI) ECL logic devices were used. These ICs were spread out over 17 modules plugged into a backplane. The VAX 8600 supported 4 to 256 MB of ECC memory and had eight slots on the backplane for memory modules. The system originally used 4 MB memory modules populated by 32 KB metal oxide semiconductor (MOS) RAMs, which limited capacity to 32 MB. Modules with larger capacities were introduced later. The memory was controlled by the M Box, which also provided the memory array bus used to access the memory. This dedicated bus, which had an 80 ns (12.5 MHz) cycle time, contributed to the improved performance the VAX 8600 had over the VAX-11/780, which accessed memory via the Synchronous Backplane Interconnect (SBI) that was shared with I/O devices. I/O was provided by the SBI. The VAX 8600 featured one SBI but could be configured with two. The SBIs were provided by SBI adapters that interfaced the SBI to an internal adapter bus connected to the M Box. Each SBI had 16 slots for I/O devices, although only 15 were usable as one slot was reserved for the SBI adapter. With one SBI, that SBI had a bandwidth of 13.3 MB/s. With two SBIs, they had a total bandwidth of 17.1 MB/s. The adapter bus that interfaced the SBIs to the M Box had a bandwidth of 33.3 MB/s. Unibus and Massbus were also supported, provided by adapters that plugged into the SBI. The VAX 8600 I/O cabinet contained a PDP-11 computer serving as the console, a Unibus card cage and provisions for mounting disk drives. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「VAX 8000」の詳細全文を読む スポンサード リンク
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